The present invention pertains in general to a digital logic bus termination technique and pertains, more particularly, to a termination module for TTL backplane busses.
In a computer system, circuit boards are typically supported from a master support board that comprises a backplane bus which, is in turn comprised of conductive runs intercoupling the various circuit boards for flow therebetween. The various bus signals are typically subject to interference and impedance mismatch problems. For example, an undesired voltage appearing at the input of a logic gate may cause an unwanted signal transition. But if the input is, for example, a logic zero, a noise signal exceeding the logic zero threshold voltage causes the device to change its state as though the input signal were a logic one. Alternatively, if the input is a logic one, a noise signal (due to reflection energy and not induced noise) that decreases the input voltage level less than logic one may cause a transition to the logic zero state.
A typical conventional approach to resolving the impedance mismatch or noise problem in TTL backplane buses is to delay sampling. In this regard the TTL backplane buses are typically designed so that a signal propagating down the bus is sampled after some fixed settling time to permit reflections caused by impedance discontinuities to attenuate to a valid logic level. However, this settling down technique results in delayed sampling rates which result in overall decreased bus bandwidths.
The ringing caused by impedance dicontinuities is illustrated in FIGS. 1A-1D. FIG. 1A illustrates the logic one to logic zero transition. FIG. 1B illustrates the same transition but with the further use of a clamping diode. FIG. 1C illustrates the logic zero to logic one transition. FIG. 1D illustrates the same transition as in FIG. 1C but again with the use of a diode clamp.
It is noted in FIG. 1A that the initial undershoot caused by a logic one to logic zero transition is followed by another reflection which is a positive overshoot. This positive overshoot can cross the logic one threshold again. If the logic level of the signal is sensed at that time then there is an incorrect logic level sensed due to this positive overshoot in FIG. 1A.
A reflection also occurs on a logic zero to logic one transition such as illustrated in FIG. 1C. However, this is less likely to occur as the output impedance of a TTL gate driving a logic one is higher (40-50 ohms) than when driving a logic zero (10-20 ohms), resulting in less impedance mismatch relative to the interconnecting transmission line. Additionally, a valid logic one region is typically higher than the logic zero region (approximately 1.5 volts vs. approximately 0.8 volts) requiring more reflection energy to force a logic one level across the logic zero threshold.
Another conventional approach to reducing mismatches is to terminate the bus at its extreme ends at an impedance closely matching the characteristic impedance of the etch trace on the bus board. Although this approach minimizes the mismatch, it does not eliminate it entirely. In this regard refer to FIG. 2 which shows the termination of the bus at its extreme ends in an impedance closely matching the characteristic impedance of the etch trace thus reducing undershoot and overshoot but not eliminating them entirely.
FIG. 3 illustrates another solution to the undershoot or overshoot problem. This is the use of clamping diodes in addition to the terminating impedance. The non-linear voltage/current characteristics of the diode clamps the voltage to within one diode drop of the reference level reducing the undershoot (logic zero to logic one case as in FIG. 1C) and the overshoot (logic one to logic zero case as in FIG. 1A).
Providing bus terminations may well require the use of terminations for 70 different signals. When employing discrete components, this makes for a relatively large terminator block that is not readily accommodated on the backplane bus. Even employing a commercially available resistor package the size of the terminating package is still too large to be readily accommodated on the backplane bus.
Accordingly, it is an object of the present invention to provide an improved digital logic bus termination that is preferably in modular form and of a size that is readiy accommodated by the backplane bus.
Another object of the present invention is to provide a logic bus termination module formed by a small circuit board, supporting on one side thereof, a connector and, on the other side, surface mounted logic means for providing diode terminations.
A further object of the present invention is to provide an improved logic bus terminating module in accordance with the preceding object and in which resistors are used in combination with the diodes with the resistors being fabricated embedded in the aforementioned circuit board.
Another object of the present invention is to provide an improved logic bus termination module that may be readily releasably plugged into the backplane to be used where needed.
Still another object of the present invention is to provide an improved digital logic termination module that employs readily available TTL logic elements that include preferably a plurality of Schottky clamp diodes to perform backplane bus clamping at the termination.
Still another object of the present invention is to provide a logic bus termination module in accordance with the preceding object and in which the module can be fabricated relatively inexpensively using a wide variety of available logic elements connected so that only the diode clamp thereof is used in the circuit.